In recent years, with the increasingly fine structure of semiconductor devices, there has been a trend for the power supply voltage driving the devices to be reduced. For this reason, the access time increases in proportion to the reduced power supply voltage, whereas for this kind of device an increase in speed together with the reduced voltage is desirable.
At the same time, as with semiconductor devices of a multi-bit construction, when there is an output circuit formed from transistors which have a large current drive ability (referred to hereinafter as "ability") with respect to an external circuit, then noise can be caused by the parasitic resistance or inductance on the power supply lines or ground lines, and this can lead to malfunctions such as the erroneous writing of data or stray oscillation.
As a means of solving these problems is known a circuit which preceding the data output sets the output lines to an intermediate potential, or the so-called intermediate potential setting circuit (referred to hereinafter as "presetting circuit"). As examples of this type of circuit may be cited, for example, Japanese Patent Application Laid-Open No. 63-112893, Japanese Patent Application Laid-Open No. 63-117839, Japanese Patent Application Laid-Open No. 8-77775 (referred to hereinafter as "the first type"), and Japanese Patent Application Laid-Open No. 2-113493, Japanese Patent Application Laid-Open No. 1-149290 (referred to hereinafter as "the second type").
In particular the structure of the first type as disclosed in Japanese Patent Application Laid-Open No. 63-112893 (referred to hereinafter as "prior art 1") is shown in FIG. 23A, an equivalent circuit for preset operation is shown in FIG. 23B, and operating waveforms thereof are shown in FIGS. 24A and 24B. It should be noted that FIG. 24A shows the case where the output capacitance C.sub.L is a low load capacitance, at approximately 30 pF, and FIG. 24B shows the case where the output capacitance C.sub.L is a high load capacitance, at 100 pF or more.
In this device, by means of a presetting circuit 200 an output terminal D.sub.out is set to an intermediate potential determined by the ability ratio of Nch transistor Q2a and Pch transistor Q1a. For example, if output terminal D.sub.out is initially high, the Pch transistor Q1a conducts, and the drain voltage DN rises, and consequently the potential of the output terminal D.sub.out falls as a result of the current I.sub.on2 and the current I.sub.on, thus being preset.
However, there are the following problems with a device of the above type.
(1) During the presetting, Pch transistors Q1a and Q6a, and Nch transistors Q2a and Q12a are all switched on, so that through currents I.sub.op2 and I.sub.on2 are generated, and the power consumption is increased. In particular this is a problem with a high voltage power supply.
(2) Again, with regard to I.sub.on2, in a multi-bit output configuration, during presetting the amount of current flowing in the internal circuits increases substantially, and this leads to problems such as the generation of noise and faulty operation in peripheral circuits.
In more detail, during the presetting, as shown in FIGS. 24A and FIG. 24B, the current I.sub.on2 becomes larger than the current I.sub.on. Here the current I.sub.on2 flows when the output terminal D.sub.out is at a potential above the threshold voltage of the Pch transistor Q1a including a voltage due to the substrate bias effect. The current I.sub.on flows when the output terminal D.sub.out is at a potential above the sum of the threshold voltage of the Nch transistor Q4a and the threshold voltage of the Pch transistor Q1a including a voltage due to the substrate bias effect.
Moreover, in a semiconductor device with a large output buffer, to prevent output noise from causing erroneous operation in the internal circuit, as shown in FIG. 23B, the method is adopted whereby V.sub.DD1 and GND1 are respectively connected to dedicated power supply pads for output drivers, and V.sub.DD2 and GND2 are respectively connected to power supply pads for internal circuits. Using this method, a relatively large current I.sub.on2 flows into the internal circuit.
It should be noted that the substrate bias effect refers to the effect that in an Nch transistor the source potential rises above the ground potential, and in a Pch transistor the source potential falls below the power supply potential, whereby the substrate is reverse biased, the threshold increases, and the channel resistance increases.
(3) When there is a large capacitance load, with the output capacitance C.sub.L being 100 pF or more, then in the interval t.sub.ACC shown in FIG. 24B, the change in the potential of the output terminal D.sub.out becomes slow, and presetting is not achieved.
The principal cause of this is that when for example the output terminal D.sub.out is high, with the fall in the potential of the output terminal D.sub.out, the Pch transistor Q1a experiences a substrate bias effect, and a sharp drop in power, so that the drain voltage DN of Q1a, which is determined by the ability ratio with respect to the Nch transistor Q2a also falls, as a result of which sufficient power is not obtained for the Nch transistor Q4a.
Again, if output terminal D.sub.out is initially low, the cause is that Pch transistor Q3a is restricted by the sum of the threshold voltage of Q3a and the threshold voltage of the Nch transistor Q2a including a voltage due to the substrate bias effect.
(4) With a low power supply voltage of 3V or less, there is insufficient operating margin for a presetting circuit, and short access times cannot be achieved with a low power supply voltage.
The principal reason for this is that in order to set the potential of the output terminal D.sub.out to an intermediate level determined by the ability ratio of the Nch transistor Q2a and the Pch transistor Q1a requires a power supply voltage of at least the sum of the threshold voltages of the transistors Q1a and Q2a each of which includes a voltage due to the substrate bias effect, and if the threshold voltages of Q1a and Q2a are set to be 0.7 V, the threshold voltages will each be raised to approximately 1.5 V, and their sum will be 3 V.
On the other hand, there is also the second type described above which has a presetting circuit configuration in which no through current flows through the pair of transistors forming the output driver. In particular the configuration of Japanese Patent Application Laid-Open No. 2-113493 (referred to hereinafter as "prior art 2") is shown in FIG. 25, and operating waveforms thereof are shown in FIGS. 26A and 26B. It should be noted that FIG. 26A shows the case where the output capacitance C.sub.L is a high load capacitance, at 100 pF or more, and FIG. 26B shows the case where the output capacitance C.sub.L is a low load capacitance, at approximately 30 pF.
In the device of FIG. 25 an output potential detection circuit 203 detects the potential level of the output terminal D.sub.out, and one of two transistors 211 and 212 which are of opposite polarity with respect to each other is operated, to set the potential level of the output terminal D.sub.out to the intermediate potential.
However, with this device, particularly when the load capacitance connected to the output terminal is a small load capacitance, such as for example 30 pF, the following problems arise.
(5) In order to operate one of the transistors 211 and 212, according to the potential of the output terminal D.sub.out, it is necessary to determine whether the potential of the output terminal D.sub.out is high or low, and thus it is necessary to detect the potential at the previously provided output potential detection circuit 203.
For example, if output terminal D.sub.out is high, then in the output potential detection circuit 203, the output of NAND gate 205 goes low, the output DN of NAND gate 207 in the output driver circuit 206 goes high, and Nch transistor 212 is switched on.
When the output capacitance C.sub.L is low, the time required for this detection is longer than the time for the potential of the output terminal to fall, when, if the output terminal D.sub.out is high, a current flows from the output capacitance C.sub.L into the Nch transistor 212. For this reason, before the NAND gate 205 of the output potential detection circuit 203 determines the output terminal D.sub.out to be low, the Nch transistor 212 causes the potential of the output terminal D.sub.out to fall at high speed, and the potential level of the output terminal D.sub.out cannot be determined definitively.
The reason that the output driver operates faster than this output potential decision is that generally in transistor drain current-drain voltage characteristics, if the gate potential is at least a threshold value, even in the region where the drain voltage is low, the current is large, and also since the load capacitance is low, this causes the time constant .tau.=RC=(V/I)C to be small.
As a result, before the output potential detection circuit 203 has determined the output terminal D.sub.out to be to be low, and switched the transistor 212 off, the output terminal D.sub.out has fallen to 0 V. Thereafter, the NOR gate 204 determines the output terminal D.sub.out to be low, and since DP goes low the Pch transistor 211 switches on. Then the output terminal D.sub.out rises at high speed, and as shown in FIG. 26B, during the preset interval the output terminal D.sub.out oscillates between the power supply potential and ground potential.
Thus, in the case of a small load capacitance, the speed with which the output driver raises or lowers the output terminal D.sub.out is higher. For this reason, during the preset interval the output oscillates, and in an output driver switching on and off at high speed, noise is generated by the current, and there are the additional problems of erroneous operation and unneeded current consumption.
(6) An example of the second type of presetting circuit, in which only one of the pair of transistors constituting the output driver is switched on, so that a through current is prevented from flowing through the pair of transistors, is disclosed for example in Japanese Patent Application Laid-Open No. 1-149290. However, in this device, a through current flows through a pair of transistors provided in a prior stage of the output driver, and similar problems to those listed above occur.
The present invention concerns the resolution of the above-mentioned technical problems, and has as its object the provision of an output circuit and electronic apparatus using the same which not only allows for short access times regardless of the load capacitance, but also eliminates the generation of a through current in the output driver, internal circuit, and so forth, and allows noise to be reduced.
Another object of the present invention is the provision of an output circuit and electronic apparatus using the same which allows for short access times even with a low power supply voltage.
Yet another object of the present invention is the provision of an output circuit and electronic apparatus using the same which, even with a presetting circuit in which no through current flows, oscillation can be prevented from occurring even when the output terminal load capacitance is low.